New clock generators deliver high performance standard for data center and consumer design

Silicon Labs offers a new family of clock generators providing what is claimed to be the industry’s lowest jitter, highest integration and lowest power consumption for applications using PCI Express (PCIe) Gen 1/2/3/4. The copmany’s new Si522xx PCIe clock generators meet the stringent requirements of PCIe Gen 4 with 20% jitter margin while providing 60% margin to PCIe Gen 3 jitter specifications. Developers can now design PCIe-compliant solutions with confidence knowing the company’s PCIe clocks maximize jitter margin and de-risk product development. Featuring PCIe Gen 4 compliance and up to 12 clock outputs, the clocks are ideally suited to provide low-jitter PCIe clock generation and distribution in data center applications, eliminating the need for standalone clock buffers. In addition to providing best-in-class jitter margin, the clocks are fully compliant with PCIe Gen 4 Common Clock and SRIS architectures. The device output drivers leverage Silicon Labs’ innovative push-pull HCSL technology, which eliminates the need for external termination resistors required by conventional PCIe clocks using constant-current output driver technology. Internal power filtering prevents power supply noise from degrading clock jitter performance, reduces component count and cuts board space by 30 percent compared to competing solutions. “Silicon Labs continues to drive innovation, performance and integration for PCI Express clocks,” said James Wilson, senior marketing director for Silicon Labs’ timing products. “With the introduction of the Si522xx family, we are now able to serve the clocking needs for the entire universe of PCIe applications, from servers and storage to industrial and consumer applications.”