Debug tool expands commercially available applications for RISC-V cores

25-09-2017 | Segger | Test & Measurement

SEGGER Microcontroller is now offering SEGGER J-Link support for SiFive Coreplex IP, based on the RISC-V architecture. The growing interest in Coreplex IP is increasingly prompting vendors to make its industry leading tools available as part of the RISC-V ecosystem. “In order to bring RISC-V and custom silicon to its full potential, the ecosystem needs a full complement of established commercial tools with which to validate designs,” said Jack Kang, vice president of product and business development at SiFive. “Support from SEGGER’s industry-leading J-Link debug probe family is a huge step for embedded developers who wish to debug software and production program chips using RISC-V cores. We look forward to our continued partnership with SEGGER and are excited to see how this development impacts the entire RISC-V community.” “RISC-V is a great CPU architecture. With various open-source and commercial implementations, we believe that it will become very popular, very fast,” said Alex Grüner, J-Link product manager and CTO of SEGGER. “J-Link’s family of professional debug probes are now available to help contribute to and build on the success of RISC-V.” Said Rick O’Connor, chairman of the RISC-V Foundation: “The fact that SEGGER is seeing commercial demand for RISC-V is evidence that open-source semiconductors are enabling a new wave of silicon design. SiFive and others implementing RISC-V cores based on SiFive’s Coreplex IP will now have the necessary tools to simplify their development workflow.”

By Electropages Admin