Ultra low-jitter clock generators enable more reliable telecoms

Texas Instruments (TI) has introduced a new family of clock generators that provides ultra-low jitter of 100 femtoseconds (fs) and flexible, 'unique' pin control options. Compared to conventional reference clock solutions, the new clock generators’ jitter performance enables system designers to optimize system timing margins and bit error rate (BER) to reduce data transmission errors. This allows for more reliable communications, networking, server, computing, and high-performance industrial equipment. LMK033x8 clock generators also offer versatile features to reduce design cycle time by facilitating easy prototype design and evaluation, says the company. Key features : 1 - Ultra low-jitter performance enables flexible jitter budgeting: Up to two high-performance PLLatinum fractional-N phase-locked loops (PLLs) with eight outputs enable ultra-low jitter performance of 100 fs root mean square (RMS) over multiple integration bandwidths (1KHz-5MHz and 12KHz-20MHz). Designers can take advantage of the ultra-low jitter to improve their system BER and increase the reliability of their telecommunications infrastructure equipment. 2 - Flexible, simple configuration: A unique pin-mode control feature enables designers to easily select from 71 pre-programmed frequency start-up plans compared to one-time programmable memory offered by competitors. Integrated electrically erasable programmable read-only memory (EEPROM) enables easy customization, while the I2C interface gives system designers complete control of device configuration. 3 - Reduced design cycle time: Glitchless fine/coarse frequency margining enables designers to simplify the stress and compliance testing of their systems during design verification and process verification (DVT/PVT) of prototypes. 4 - Immune to supply noise: Integrated low-dropout regulators (LDOs) provide immunity to power-supply noise without requiring complex filter designs. Evaluation modules (EVMs) enable designers to quickly and easily evaluate the devices. The LMK03328EVM is available now, and the LMK03318EVM will be available in 4Q 2015. TI’s WEBENCH Clock Architect tool simplifies the design process for the LMK033x8 family, as well as for other TI clock and timing devices. The tool can recommend a single- or multiple-device clock-tree solution from a broad database of devices to meet system requirements. It features PLL filter design, phase-noise simulation, and the ability for designers to optimize clock-tree designs for their performance and cost requirements, says the company.