SDRAM uses a double data rate architecture to achieve high-speed operation

24-07-2015 | Mouser Electronics | Semiconductors

Employing a double data rate architecture to achieve high-speed operation, Alliance Memory's DDR3L SDRAM is now available from Mouser stock. The double data rate architecture uses an 8n-prefetch architecture with an interface de-signed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
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By Craig Dyball