11-07-2017 | | By Paul Whytock
In a major technological development a material-device-circuit level co-optimisation of field-effect transistors (FETs) based on 2D materials for high-performance logic applications scaled beyond the 10nm technology node has been presented.
It is the result of collaborative work between Imec, the nanoelectronics and digital technology innovation centre and scientists from KU Leuven in Belgium and Pisa University in Italy. In addition to this Imec has also created designs which are thought to allow the use of mono-layer 2D materials to facilitate Moore’s law below a 5nm gate length.
Scientists believe 2D materials which are formed from two-dimensional crystals may be able to create a transistor with a channel thickness down to the level of single atoms and gate lengths of a few nanometers.
A key technology driver that allowed the chip industry to progress Moore’s Law and to producing increasingly powerful devices was the continued scaling of gate lengths.
In order to counter the resulting negative short-channel effects, chip manufacturers have already moved from planar transistors to FinFETs. They are now introducing other transistor architectures such as nanowire FETs. This material breakthrough goes beyond existing practices.
In order to fit FETs based on 2D materials into the scaling roadmap it is essential to understand how their characteristics relate to their behavior in digital circuits. In a recent paper published in Scientific Reports the Imec scientists and their colleagues explained how to choose materials, design the devices and optimise performance to create circuits meeting the requirements for sub-10nm high-performance logic chips. Their findings demonstrate the need to use 2D materials with anisotropic characteristics, meaning it is stronger along its length than laterally and also has a smaller effective mass in the transport direction.
Using one such material, monolayer black-phosphorus, the researchers presented device designs which they say could pave the way to extend Moore’s law into the sub-5nm gate length.
These designs reveal that for sub-5nm gate lengths, 2D electrostatics arising from gate stack design become more of a challenge than direct source-to-drain tunneling.
These results are very encouraging because in the case of 3D semiconductors, such as Si, scaling gate length so aggressively is practically impossible.