12-10-2016 | | By Paul Whytock
A technology breakthrough that removes the need for dynamic random memory (DRAM) refresh and is claimed to provide power, efficiency and compatibility benefits has been unveiled by US non-volatile memory specialists Kilopass.
Based on vertical layered thyristor (VLT) technology, this structure is electrically equivalent to a cross-coupled pair of bipolar transistors that form a latch, a circuit that has two stable states and can be used to store information. This, says the company, is particularly suitable for memory applications compared to capacitor-based DRAM technology and does not require refresh.
Thyristor technology is nothing new it was invented seventy years ago and many attempts have been made to use it for the SRAM market. This VLT is based on implementing the thyristor structure vertically.
Because VLT does not require complex performance and power-consuming refresh cycles, a VLT-based DDR4 DRAM lowers standby power by a factor of ten when compared to conventional DRAM at the same process node. Furthermore, VLT requires fewer processing steps and is designed to be built using existing processing equipment, materials and flows.
The VLT bitcell operations and silicon measurement have exhibited good correlation to the company’s proprietary TCAD simulator that is one hundred thousand times faster than a traditional TCAD simulator.
The TCAD simulator enables Kilopass to predict the manufacturing windows for key process parameters, and optimise the design for any manufacturing process.The DRAM market is being driven by strong demand in the server/cloud computing market as mobile phone and tablet market growth are slowing and computing is moving increasingly to the cloud. Kilopass says the future for DRAM growth remains strong.
In a report published in 2015, IC Insights forecasts DRAM CAGR of 9% over the period from 2014 – 2019. If correct this DRAM rate could indicate faster growth for the memory sector than the general IC market.
Servers and server farms consume copious quantities of energy with memory being a large contributor. Kilopass believes the current generation of 20nm DRAM should migrate to sub-20nm processes to deliver even lower power.
However, current DRAM technology is based on the 1 transistor, 1 capacitor (1T1C) bitcell and is difficult to scale since the smaller transistors exhibit more leakage and the smaller capacitor structure has less capacitance, resulting in the need to reduce the time between refresh intervals. Up to 20% of a 16Gb DDR DRAM’s raw bandwidth will be lost due to the increased frequency of refresh cycles, a negative for multi-core/multi-thread server CPUs that must maximise performance to remain competitive. Consequently the DRAM industry needs to increase memory performance while reducing power consumption.