EnSilica and BaySand cooperate on configurable MPW IP solutions

18-08-2016 |   |  By Paul Whytock

Semiconductor and intellectual property company EnSilica has agreed to provide configurable ASICs specialist BaySand’s ASIC UltraShuttle-65 multi-project wafer (MPW) customers with a range of configurable intellectual property (IP) solutions.

BaySand recently announced the availability of the ASIC UltraShuttle-65 silicon MPW program that supports multiple designs customisable by four metal layers. The methodology is based on BaySand’s standard cell library, including logic cells, IOs, memories and IP blocks that the company says are fully characterised and silicon proven.

The IP provided by EnSilica will comprise the company’s eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware accelerators.

Complex CPU Subsystems

EnSilica says its automated flow allows complex CPU sub-systems to be delivered to customers quickly and can include single or multiple eSi-RISC processor cores with JTAG debug, a range of peripherals and timers and encryption accelerator cores.

The system is designed around standard multi-layer AMBA AHB bus fabric generated as part of the automated flow. Additional APB, AHB, AXI buses can be included to allow the simple integration of the customer’s own IP cores. This design flow is expected to allow EnSilica processor sub-systems to be delivered to customers ahead of the first ASIC UltraShuttle-65 MPW run in October 2016.

The ASIC UltraShuttle-65 MPW can also be used for FPGA to ASIC conversion which is said to cut risk and costs while shortening time to market.

RTOS Partner

EnSilica also recently partnered with Micrium the RTOS provider to port Micrium’s µC/OS-III RTOS to EnSilica’s family of eSi-RISC processor cores.

Micrium’s range of communication software, including its USB host/USB device and TCP/IP networking protocol stack, has been ported to EnSilica’s eSi-RISC.

Micrium’s µC/OS-III is a pre-emptive and deterministic multi-tasking RTOS with optional round-robin scheduling. It is claimed to be capable of supporting unlimited application tasks and kernel objects.

EnSilica and BaySand cooperate on configurable MPW IP solutions


By Paul Whytock

Paul Whytock is Technology Correspondent for Electropages. He has reported extensively on the electronics industry in Europe, the United States and the Far East for over thirty years. Prior to entering journalism, he worked as a design engineer with Ford Motor Company at locations in England, Germany, Holland and Belgium.

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