Chip breakthrough will accelerate development of self-drive cars

16-12-2015 |   |  By Paul Whytock

A new SRAM that could provide the real-time image processing capabilities for future autonomous-driving technologies has been developed by Renesas Electronics.

The company has revealed that when testing the new SRAM in a 16nm process, it managed 688 picosecond high-speed operations within a voltage condition of 0.7V and a high-level integration density of 3.6 Mbit/mm.

Automotive developments like driver assistance technology and satellite systems require high-level real-time image processing technologies in order to be both feasible and safe in operation.

Improvements in system performance has typically been achieved by the creation of algorithms that produce more precise images.

The dual-ported on-chip SRAM designed by Renesas can now work with these algorithms because it can perform write and read operations simultaneously to achieve approximately twice the performance of standard single-ported on-chip SRAM.

However, compared to the single-ported SRAM, this dual-ported SRAM suffers from several problems, including not only requiring more chip area, but also increased power consumption when access speeds are increased, worse lower limit voltage margins, and other issues.

These operational difficulties have been resolved by adopting a dual-ported SRAM memory cell optimised for FinFET devices. Renesas has also applied a word line boost type assist circuit technology developed for single-ported SRAM to enable high-speed read and write operations that are stable at lower voltages and allow power consumption to be suppressed in a small chip area.

Key operating characteristics of the new SRAM include, word line overdrive type assist circuit, which takes advantage of the features of the FinFET device and achieves low-voltage high-speed operation and adoption of memory cell optimal for dual-ported SRAM which achieves integration density if 3.6 Mbit/mm.

Unlike single-ported SRAM, for dual-ported SRAM there are various layout topologies for the bit cell. Although a planar MOSFET structure has been used until now in 28nm processes, Renesas has adopted a new FinFET device, which provides a fin structure that suppresses process variations in the 16nm process and improves device characteristics. This new FinFET device does have very precise layout restrictions and it is difficult to use the layout structure that was optimal for earlier planar type devices.

Also, a symmetrical layout structure is needed for stable operation because MOS characteristics are prone to extreme variations. In this new SRAM, Renesas has optimised the design of the peripheral circuits as SRAM for real-time image processing.


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By Paul Whytock

Paul Whytock is European Editor for Electropages. He has reported extensively on the electronics industry in Europe, the United States and the Far East for over twenty years. Prior to entering journalism he worked as a design engineer with Ford Motor Company at locations in England, Germany, Holland and Belgium.

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