FPGA-based wearable device development platform breaks down size barriers

Three design imperatives when it comes to creating wearable devices for consumers are low power consumption, compact size and a list of functions that will unnerve competitors.

In a new development American chip maker Lattice Semiconductor has created an FPGA-driven wearable design platform which it says is 60% smaller that alternative microcontroller designs Lattice.

The platform is based on the iCE40 Ultra FPGA which features a range of sensors and peripherals and also supports a low power standby mode for always-on functionality.

Hardware features and sensors supported by the iCE40 Ultra Wearable Development Platform include a 1.54in display, MEMS microphone, high-brightness LED, IR LED, BLE module and 32MB of flash memory.

The platform also supports sensors capable of measuring heart rate/SpO2, skin temperature as well as an accelerometer and gyroscope.

The platform comes in a wrist watch form factor (1.5-inches wide x 1.57-inches long x 0.87-inches high) with a wrist strap and an integral battery.

These FPGAs offer up to 3520 LUTs and up to 26 I/O's for customised interfaces. Integrated hard IP and programmable logic enables quick customisation. The device can handle IR remote functions, barcode reading, touch sensing and user identification.

Other features include:

• Programmable I²C & SPI interfaces.
• 10kHz low power scillator.
• 48MHz high performance oscillator.
• Four 16 x 16 multiplier & 32bit accumulator blocks.
• Programmable PLL.
• Three 24mA constant current sinks.
• One 500mA constant current ink.
• Up to 80kbits of embedded block non-volatile RAM.