18-11-2015 | | By Sally Ward-Foxton
Cadence has unveiled the Palladium Z1, an emulation platform with a capacity of up to 9.2 billion gates which can support up to 2034 parallel jobs. The new emulator has 5x the throughput of its closest competitor, says Cadence, calling it the industry’s first datacentre-class emulation system.
“Emulation is moving towards becoming the centre of verification,” said Michal Siwinski, VP of Product Management in the System & Verification Group at Cadence. “Verification and software account for 70% of the total cost of [chip] development, while 80% of EDA investment historically has been in implementation. This automation gap is holding back innovation.”
Compared to implementation, verification and software were historically harder to automate so there is still a gap between how much customers spend on these parts of the process compared to how much EDA companies are investing there. Cadence is aiming to try to close the gap with bigger and better emulator platforms like the Palladium Z1. Capacity has been increased from 2.3bn (the Palladium XP II) to 9.2bn gates after customers complained that 2 billion gates was not enough, Siwinski said; 2 billion was just enough to meet present demands, but customers have 4 or 5 billion gate chips on their roadmaps.
The Palladium Z1 has a rack-based architecture to improve reliability – blades can be hot swapped if something goes wrong or capacity added or removed as needed. It also offers a third of the power consumption per emulation cycle of its predecessor, the Palladium XP II, down to a combination of reducing power density 44% and increasing throughput performance. Other benefits include a 92% smaller footprint and 8x higher gate density than the XP II.