18-08-2015 | | By Paul Whytock
What is claimed as the world’s first 32Gbytes 48-layer BiCS FLASH device with a three-dimensional (3D) stacked cell structure has been developed and launched by the Toshiba Corporation.
It features triple-level cell (TLC) technology which is a type of solid-state NAND flash memory that stores three bits of data per cell of flash media. One of the major advantages of TLC is it is cheaper than single-level cell (SLC) and multi-level cell (MLC) solid-state flash memory.
A world of firsts
But this is not the only world first currently claimed by Toshiba. It has also announced the development of the first 16 die stacked NAND flash memory that uses through silicon via (TSV) technology. But more on that later.
Getting back to the TLC technology, each of the three bits of data in a TLC flash cell is either programmed (0) or erased (1). This means the cell has eight different states.
When we look at an MLC cell it contains two bits of data compared to the one bit of data in an SLC cell. What TLC flash does is add an extra bit of data per cell which is why the TLC has 50% more storage than MLC flash.
In addition, a TLC flash die contains the same capacity as an MCL flash die but is smaller and this is why it is more cost efficient. An array of 16 billion SLC cells holds 16 Gbytes of data compared to an array with 16 billion MLC cells which has a capacity of 32 Gbytes.
As previously mentioned, BiCS FLASH is based on a 48-layer stacking process that outguns the capacity of mainstream two-dimensional NAND Flash memory while boosting write speeds.
Through silicon via technology
Returning to the earlier mentioned NAND flash memory that uses through silicon via (TSV) technology, this design approach uses the vertical electrodes and vias to pass through the silicon dies for connections. The operational advantage of this approach is it enables high-speed data input and output and cuts power consumption.
TSVs are a high performance interconnect technique used as an alternative to wire-bond and flip chips to create 3D packages and 3D ICs, Fundamentally, the density of the vias is much higher and the length of the connections shorter.
In most 3D package designs the stacked chips are wired together at their edges which increases the length and width of the package and usually requires an extra layer between the chips.
Toshiba’s says its TSV technology achieves an I/O data rate of over 1Gbps which it believes is higher than any other NAND flash memories with a low voltage supply of 1.8V to the core circuits and 1.2V to the I/O circuits. In terms of power reduction the company maintains this design cuts consumption by half.
But what specifiers and purchasers will want to know is when will this technology hit the streets? Well, Toshiba is busy preparing a new Fab2 at Yokkaichi Operations which is its manufacturing facility for NAND flash memories. It's expected that Fab2 will be ready to go in the first half of 2016.