24-08-2015 | | By Alan Elbanhawy

*Getting a few more percentage points of efficiency from a DC/DC supply is a challenge, but a two-stage converter with a dynamically optimised intermediate bus voltage offers a solution. By Alan Elbanhawy, Exar Corporation*

Achieving efficiency in DC/DC power supply converters is among the priorities for most projects, to reduce heat dissipation and operating costs while also meeting regulatory requirements. The efficiency of these supplies has been steadily climbing and is now reaching the mid 90% level in some cases. Getting that number higher will take some new approaches.

There are several challenges when converting a medium-range DC voltage in a single stage from a rail ranging between 36V and 48V to an intermediate DC voltage such as 5V or 1V. The result is higher power losses than acceptable, along with lower efficiency and higher thermal load in the final application.

These intermediate-voltages are then converted further down to multiple distinct values typically between 0.6 V and 3.3V, as supply rails for the CPU, FPGA, DDR memory and other components. However, despite the present focus on high efficiency over the entire range of the load currents in these multi-rail systems, the intermediate voltages of 5V or 12V may not be optimum for all loads.

Overcoming this challenge may lead to more complex and larger implementation of the power section. In today’s extremely aggressive markets, where all new applications must be more powerful, have smaller size, be lighter weight and be less expensive than the competition, a new solution is needed. To meet the requirements, Exar has developed a new IC that enables a two-stage bus architecture, which facilitates achieving high efficiency where there is a need to convert higher DC voltages into much lower voltage and at high load currents.

**Analysis is first step**

The losses and loss mechanisms in synchronous buck converters can be divided into the following categories:

- Conduction losses due the MOSFET on-resistance RDS(ON), which are proportional to the square of the RMS drain current
- Dynamic or switching losses in the MOSFET, which are proportional to the switching frequency, drain-source voltage, drain current and rise and fall times of both drain-source voltage and drain current
- Losses due to the DC resistance (RDC) of the inductor, which are proportional to the square of the RMS inductor current
- Miscellaneous losses such as gate-driver capacitive losses, reverse-recovery losses and losses due to parasitic inductance and stray capacitance

Note that almost all the losses are proportional to currents and voltages. Since the currents are dictated by the load demands, an adaptive dynamic adjustment of the two-stage voltages can yield conditions for minimum losses for a given load current.

The total loss equation can be used to derive the best operating voltage for the intermediate stage. In applications where the load current is varying continuously and rapidly, a fast and precise architecture and algorithm is mandatory.

To achieve the best overall efficiency possible, the intermediate voltage needs to be continuously and dynamically adjustable. Monitoring both the input and output voltages and currents and then using an algorithm to calculate the intermediate voltage that results in the best efficiency, based on the instantaneous input and output parameters of the converter, can achieve this. This calculation is done dynamically "on the fly" and is performed at a programmable rate that fits the application.

The switching frequency of each of the two stages in this architecture must be selected to further enhance the results. Typically, the first stage will operate at a lower frequency to minimize the switching losses of the high-side MOSFET, while the switching frequency of the second stage can be higher to achieve the desired transient response without any compromise.

A further refinement of the process is to shift the converter between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) modes, also on the fly, to achieve the best possible efficiencies from very low load currents to full load. This approach requires two control loops, with the loop that controls the intermediate voltage continuously adapting to the new output current to achieve good transient response. Ideally, a single IC could be designed to accommodate both the intermediate- and end-voltage converters. The provider should also offer a design tool to help with the selection of control-loop parameters to achieve the best-possible loop bandwidth and transient response.

**Design Approach**

The two-stage synchronous buck converter (Figure 1) used in the evaluation of this approach shows all the components that contribute to the system losses. The goal is to dynamically determine the best intermediate voltage.

A mathematical model was compiled using Maplesoft's Maple math engine to analyse the dependency of the optimum intermediate voltage on the overall losses. The simplified equation set (see"Losses versus Intermediate voltage", below) shown provided results that were very close to the more detailed equation. These were used to plot losses for load currents from 5A to 30A (Figure 2) clearly showing the different intermediate voltages resulting in minimum loss as a function of load current.

Figure 3 shows the efficiency advantages of this architecture, using the values of the optimum intermediate voltage previously plotted. Switching frequency for first stage is 200kHz and 500kHz for the second stage; the first stage input is 36V, the second stage output is 1.2V and the maximum output current is 22A.

The improvement in efficiency at maximum load current translates directly into higher reliability, as a result of the lower operating temperature (as a general guideline, every 10°C decrease in the temperature translates to doubling the mean time between failures (MTBF). The lower thermal load also results in cost savings in the cooling-system requirements. As demonstrated here, a dynamic two-stage system can be made to operate much more efficiently without any additional components compared to the traditional, static two-stage approach.

**Losses versus Intermediate voltage**

The analysis begins with loss equations of all MOSFETs in Figure 1:

Where:

- MHS1Losses, MLS1Losses, MHS2Losses and MLS2Losses are the respective losses in MHS1, MLS1, MHS2 and MLS2;
- IL1 and IL2 are the load currents on the intermediate stage and the second stage;
- ∧s1 and ∧s2 are the duty ratios for intermediate stage and the second stage;
- τrf is the rise/fall times of the switching MOSFET;
- τdeadtime is the deadtime between the control and synchronous MOSFETs drives.

The losses in the inductors L1 and L2 are Pind1 and Pind2:

The first and second stage duty cycles ∧s1 and ∧s2 can be calculated from the following equations:

For the total losses, add equations 1 through 5:

These results are then used derive the equation for optimum intermediate voltage that yields the smallest losses for any given load current.

**References**

[1] Barry, M., “Design issues in regulated and unregulated intermediate bus converters,” Nineteenth Annual IEEE APEC 2004.

[2] Sayani, M.P., Wanes, J., “Analyzing and determining optimum on-board power architectures for 48 V-input systems,” Eighteenth Annual IEEE APEC 2003.

[3] Rais Miftakhutdinov, “Power distribution architecture for tele- and data communication system based on new generation intermediate bus converter,” IEEE 30th International INTELEC 2008.

[4] David G. Morrison, “Distributed Power Moves To Intermediate Voltage Bus,” Electronic Design, September 16, 2002.

[5] Alan Elbanhawy, “Buck converter losses under the microscope,” Power Electronics, February 1, 2005.