World’s largest FPGA-based adaptive SoC for emulation and prototyping

03-07-2023 | AMD | Semiconductors

AMD has announced the AMD Versal Premium VP1902 adaptive SoC, the world’s largest adaptive SoC. The VP1902 adaptive SoC is an emulation-class, chipset-based device created to streamline the verification of increasingly complex semiconductor designs. Offering 2X2 the capacity over the prior generation, designers can confidently innovate and validate ASICs and SoC designs to help bring next-generation technologies to market faster.

AI workloads are driving increased complexity in chipmaking, demanding next-generation solutions to develop the chips of tomorrow. FPGA-based emulation and prototyping supply the highest level of performance, allowing faster silicon verification and allowing developers to shift left in the design cycle and begin software development well before silicon tape-out.

“Delivering foundational compute technology to enable our customers is a top priority. In emulation and prototyping, that means delivering the highest capacity and performance possible,” said Kirk Saban, corporate vice president, Product, Software, and Solutions Marketing, Adaptive and Embedded Computing Group, AMD. “Chip designers can confidently emulate and prototype next-generation products using our VP1902 adaptive SoC, accelerating tomorrow’s innovations in AI, autonomous vehicles, Industry 5.0 and other emerging technologies.”

As complexity grows in ASIC and SoC designs, particularly with the fast advancement of AI and ML-based chips, extensive verification of silicon and software before tape-out is a must. The new SoC provides industry-leading capacity and connectivity, supplying 18.5M logic cells for 2X2 higher programmable logic density and 2X4 aggregate I/O bandwidth than the previous generation Virtex UltraScale+ VU19P FPGA.

The adaptive SoC leverages the Versal architecture, including the programmable network-on-chip, to deliver up to 8X5 faster debugging than the prior generation VU19P FPGA.

The AMD Vivado ML design suite supplies customers with a comprehensive development platform to quickly design, debug and validate next-generation applications and technologies and accelerate time to market. New features that support more efficient development on the adaptive SoC comprise automated design closure assistance, interactive design tuning, remote multi-user real-time debugging, and enhanced back-end compilation, which enables end users to iterate IC designs faster.

The company collaborates closely with the EDA community to enable customers to turn their innovations and technology vision into reality. Working closely with the top EDA vendors, including Cadence, Siemens, and Synopsys, allows designers to access an ecosystem of fully-featured and scalable solutions.

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By Seb Springall

Seb Springall is a seasoned editor at Electropages, specialising in the product news sections. With a keen eye for the latest advancements in the tech industry, Seb curates and oversees content that highlights cutting-edge technologies and market trends.