New solution delivers up to 10x faster concurrent full-chip optimisation and signoff

17-10-2022 | Cadence | Semiconductors

Cadence Design Systems, Inc now offers the new Cadence Certus Closure Solution to manage growing chip-level design size and complexity challenges. The solution environment automates and accelerates the entire design closure cycle from weeks to overnight – from signoff optimisation through routing, STA and extraction. The solution supports the largest chip design projects with unlimited capacity whilst substantially enhancing productivity by up to 10X versus current methodologies and flows.

The solution reduces the design signoff closure bottlenecks and complexities of developing today’s emerging applications like hyperscale computing, mobile, 5G communications, automotive and networking. Before the introduction of the solution, a full-chip closure flow involved manual, tedious processes from full chip assembly, static timing analysis, and optimisation and signoff with 100s of views, taking designers months to converge. The new solution delivers a fully automated environment that is hugely distributed for superior optimisation and signoff. This permits concurrent, full-chip optimisation through an engine shared with its Innovus Implementation System and the Tempus Timing Signoff Solution, eradicating iterative loops with block owners while allowing designers to make rapid optimisation and signoff decisions. Also, with the Cadence Cerebrus Intelligent Chip Explorer, designers can experience further productivity improvements from block-level to full-chip signoff closure.

“Today’s design teams often spend five to seven days per iteration to meet chip-level signoff timing and power requirements, and previous methodologies failed to deliver the team collaboration and user experience needed for efficient design closure,” said Dr Chin-Chi Teng, senior vice president and general manager in the Digital and Signoff Group at Cadence.

“We are intensely in tune with the needs of the design community, and with the release of the new Cadence Certus Closure Solution, we’re offering our customers a novel environment for chip-level optimisation and signoff that delivers exceptional PPA results within a matter of hours. With this new Cadence solution, we’re empowering customers to achieve productivity goals and deliver products to market faster.”

The solution supports the company’s Intelligent System Design strategy, facilitating design excellence.


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