Cadence Design Systems, Inc has announced that Arm is leveraging Cadence Liberate MX Trio Characterisation to enhance the quality of its embedded memory instances and compilers and quicken time to market. With Liberate MX Trio Characterisation, Arm fulfilled its accuracy and capacity needs and decreased memory liberty variation format (LVF) characterisation validation runtime by 7X compared with brute-force Monte Carlo simulation.
The solution is a library characterisation answer ideal for large, advanced-node memory designs. It enables the Arm engineering team to perform characterisation validation of its embedded memory instances and compilers efficiently and accurately. Unlike conventional solutions that need trade-offs between runtime and accuracy, it provided Arm with automated and simulation-based dynamic partitioning to lower runtime, improve capacity and sustain SPICE-level accuracy. Also, its probing capabilities aided Arm in identifying the most critical timing arcs and decreased the manual effort associated with characterisation path selection. Simulations on the full RC netlist covering an entire vector set let Arm identify accurate worst-case paths and sustain SPICE-level accuracy. Moving from Arm’s prior brute-force Monte Carlo simulation methodology to the Liberate MX Trio Characterisation variation LVF analysis methodology saved it weeks of validation time via the solution’s automated and less error-prone methodology.
“Arm has been leveraging the Liberate Trio Characterization Suite for standard cell characterisation, so it was an easy choice for us to broaden our deployment with Liberate MX Trio Characterization to address our evolving LVF memory characterisation needs,” said Philippe Moyer, VP Design Enablement, Physical Design Group, Arm. “By incorporating Liberate MX Trio Characterization into our methodology, we are improving accuracy, capacity and meeting time-to-market goals with the delivery of our embedded memory instances and compilers.”
“Memory characterisation can have a significant impact on signoff accuracy, and Arm was looking for a reliable solution for its embedded memory IP that would help them achieve their accuracy requirements while speeding time to market,” said Sharad Mehrotra, VP of R&D, in the Digital and Signoff Group at Cadence. “Arm joined a community of successful, production-proven Liberate MX Trio Characterization customers, trusting the solution for its memory characterisation needs and expanding upon its use of the broader Liberate product portfolio for standard cell power and performance characterisation.”