Application note on how to reduce RF interference currents effectively

19-07-2022 | Wurth | Passives

With its Application Notes, Würth Elektronik deals in detail with challenging issues regarding the design of circuits, providing valuable tips for practical applications. This new Application Note, ANP098 "Effect of layout, vias and design on the blocking quality of filter capacitors", is aimed at blocking capacitors, which filter out higher frequencies from the signal path by deriving RF signals superimposing a DC current against ground. Employing real measurements and practically realistic simulations, PCB-layout techniques for filter and blocking capacitors are also described as ideal for the supply pins of digital ICs.

This Application Note was written by Field Application Engineer Andreas Nadler, Würth Elektronik eiSos, Business Unit, for passive and active components and who is responsible for the EMC-conform design of power-supply systems and the suppression screening of electronic modules. In his AppNote, Nadler describes the effects of layout, vias, and design on the blocking quality of filter capacitors, a topic that is otherwise dealt with in handbooks only at the theoretical level.

The fundamental task of blocking capacitors on supply pins is to short-circuit the digital circuits' clocked current loop locally using a low impedance. This reduces the radiated magnetic field strength and the RF interference currents coupled into the supply voltage level as much as possible. Suppose the capacitors are optimally selected concerning their impedance curve and geometrically optimally placed at the VCC pins. In that case, the clocked RF current can be blocked in the best possible way.

The new app note aims to illustrate the MLCC design's influence, the number of ground vias, and the filter components' placement on each other. In addition, it is clearly shown how unexpected problems can arise due to the unfortunate dimensioning of capacitor banks.

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