SoC design suite delivers significant productivity gains

30-01-2019 | MicroSemi | Semiconductors

As each new generation of devices scale, FPGA designs are growing in complexity and resource utilisation, making designer productivity crucial to expediting time to market. Microsemi has released the Libero SoC version 12.0, providing new gains in runtime and quality of results, as well as one combined design suite for all the company’s current-generation FPGA families, incorporating new production releases of PolarFire FPGAs.

“Libero SoC v12.0 is the result of our determination to offer a comprehensive, easy-to-adopt, easy-to-learn FPGA design suite,” said Rajeev Jayaraman, vice president of software for the FPGA business unit at Microchip’s Microsemi subsidiary. “This latest release is focused on delivering the many essential elements needed for efficient design implementation, while further enabling the growing adoption of the low-power PolarFire family across each of our key market segments.”

The new release also improves DDR memory performance by an average of 29% in high-effort mode and 39% in regular-effort mode. Enhanced TCL support allows a much-requested feature where customers can run the complete design flow on the command line if they so choose.

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