Collaboration to deliver first integrated FIL workflow for FPGA development boards
Microsemi Corporation has announced its collaboration with MathWorks to launch hardware support for FPGA-in-the-loop (FIL) verification workflow with Microsemi FPGA development boards. The new integrated FIL workflow with HDL Coder and HDL Verifier from MathWorks allows customers to automatically produce test benches for HDL verification, including VHDL and Verilog, offering rapid prototyping and verification of designs.
The collaboration with MathWorks allows customers to integrate MATLAB, a programming environment for algorithm development, data analysis, visualization and numeric computation, and Simulink, a graphical environment for simulation and Model-Based Design, with the company's SmartFusion2 SoC FPGA and PolarFire FPGA development boards, allowing the stimulation of designs through FIL verification workflow using their development boards. FIL verification workflow allows clients to analyse the results back in MATLAB and Simulink.
Shakeel Peera, vice president FPGA marketing for Microsemi commented: “With the ever-increasing complexity in algorithm designs, it has become imperative for designers to quickly design and validate their algorithms on real hardware. This integrated FPGA-in-the-loop workflow of Microsemi FPGA boards with MathWorks HDL Verifier will allow system engineers and algorithm developers to quickly prototype and implement their MATLAB and Simulink designs on Microsemi FPGA development boards through our Libero SoC Design Suite.”
“MATLAB and Simulink are widely used by engineers to develop algorithms targeting FPGAs,” said Paul Barnard, director of marketing for the Simulink product family at MathWorks. “Now that HDL Verifier supports FIL for Microsemi development kits; engineers can connect designs implemented on these FPGA boards directly to MATLAB and Simulink test benches, streamlining a crucial validation step in developing safety-critical avionics, space and other applications.”