What’s all this game-changing MRAM gizmo-tech about – anyway? Jun 20 2018 Electroblog Print Article Jun 20 2018 Electroblog MRAM (magnetoresistive random-access memory) technology has been around for the past 30 years but recent developments could make it the go-to memory tech. Why is that? The major developmental reasons relate to speed, density and those all-important power consumption considerations. And a recent manufacturing breakthrough could provide those factors at a sufficient level to suit modern applications. It now looks like it’s possible to produce spin-orbit torque MRAM (SOT-MRAM) devices via a CMOS process on 300mm wafers which provides performance characteristics that could see it replacing SRAM memories in a lot of demanding applications such as high-speed computing. And this speed element is important. Conventional DRAM devices are somewhat hindered by the rate at which stored information in its cells can be read or written. This is just one of the areas where MRAM devices have the upper hand. Fundamentally, a material is considered to be magnetoresistive if it demonstrates changes in electrical resistance when placed in a magnetic field. MRAM devices work by measuring voltages rather than charges or currents and consequently require less settling time to the extent that access times on certain MRAM devices have been as fast as 2ns. But what exactly is this recent development that has boosted MRAM operating characteristics? Until now SOT-MRAM devices have been purely laboratory experiments but research centre Imec has created proven full-scale integration of SOT-MRAM device modules on 300mm wafers using a CMOS-compatible processes. Central to the design of the SOT-MRAM device is a magnetic tunnel junction in which a thin dielectric layer is held between a magnetic fixed layer and a magnetic free layer. Similar as the STT-MRAM variant in operation, writing of the memory is performed by switching the magnetisation of this free magnetic layer by means of a current. In STT-MRAM, this current is injected perpendicularly into the magnetic tunnel junction, and the read and write operation is performed through the same path. This say experts can possibly impact negatively on device reliability. However, in an SOT-MRAM device, switching of the free magnetic layer is done by injecting an in-plane current in an adjacent SOT layer and because of the current injection geometry the read and write path are de-coupled This says Imec significantly improves device endurance and read stability. Imec has compared SOT and STT switching behavior on devices fabricated on 300mm wafers. While switching speed during STT-MRAM operation was limited to 5ns, reliable switching down to 210ps was demonstrated during SOT-MRAM operation. The SOT-MRAM devices show unlimited endurance (>5×1010) and operation power as low as 300pJ. At present four foundries plan to offer MRAM as an embedded memory solution. They are GlobalFoundries, Samsung, TSMC and UMC and they plan to start providing STT-MRAM. However, given the groundbreaking work by Imec it looks like SOT-MRAM will come hot on the heels of that. By Paul WhytockPaul Whytock is European Editor for Electropages. He has reported extensively on the electronics industry in Europe, the United States and the Far East for over twenty years. Prior to entering journalism he worked as a design engineer with Ford Motor Company at locations in England, Germany, Holland and Belgium.