Higher Integration Solves the Challenges in Advanced Clocking Applications

In applications that require highly accurate clocks, there are several alternatives for meeting the combination of frequency accuracy, ultra-low phase jitter and high fan-out, by Juan Conchas, Marketing Director, Micrel.

While it is true that almost all electronic devices require a clock, only certain applications require stringent control of parameters such as phase jitter, spurious content and frequency accuracy. Communications applications, for example, whether over wireless, coaxial, twisted pair or fibre optic media, have tight requirements of clocking parameters in order to enable a robust link. As engineers strive to achieve ever-higher data rates and increased port count, the requirements on the source clock become even more stringent. Engineers inevitably struggle to find solutions that address all the requirements while delivering the performance necessary to maintain excellent link integrity. Using clock generators that are more highly integrated can ease the design challenges presented to engineers. This article will focus on the various challenges engineers face while trying to meet the higher data rates and discuss various trade-offs associated with each option.

Challenges engineers face while trying to meet the higher data rates

Engineers typically face three major challenges when considering today’s trend of higher port density and higher data rates. The first challenge is to generate a clock signal that meets the output centre frequency and frequency accuracy of the communications protocol. The second issue is that the signal must meet the phase noise or phase jitter requirements specified by the processor, SERDES or ASIC manufacturer. And the final trial is that a higher port count requires fanning out the clock signal to multiple ICs while minimising phase noise degradation, which is introduced by compounding multiple stages of fan-out or signal level translations.

Engineers typically fall back on quartz technologies to solve the first challenge of generating a stable and low noise output frequency. There are, of course, other technologies, including MEMS (micro electromechanical systems). However, quartz offers the engineer the benefits of high Q-factor, self-compensation over temperature and reliability. A good Q of >100,000 enables low close-in phase noise that readily meets -70dBc/Hz at 10Hz offset. Lower phase noise can be achieved using special techniques. The self-compensating qualities of the crystal lattice maintain resonant frequency within +/-10 to +/-20 parts per million (PPM) from -40°C to +85°C, again meeting the requirement of most communications applications. The crystal only needs to be externally temperature compensated if stability below +/-10PPM needs to be guaranteed. Moreover, since quartz has been manufactured in high volume for decades, failure modes have been weeded out of the manufacturing process, making this choice reliable and robust.

The most commonly available quartz resonators operate with a fundamental frequency between 10MHz and 80MHz. Although suppliers for these frequencies are abundant, growing and processing quartz crystals remains a long lead-time endeavour, so careful supply chain management is necessary. Industry-wide shortages are frequent and largely unpredictable as the capacity for crystal manufacturing may be occupied by a few high-volume applications such as mobile phones. Supply chain management of quartz crystals can be daunting, especially for smaller organisations that may not have direct relationships with large crystal suppliers.

Many communications links rely on higher frequency references, such as 156.25MHz for Ethernet or 212.5MHz for Fibre Channel. The challenges compound for crystals above 80MHz since distinct manufacturing technology is necessary, and fewer crystal suppliers support this frequency range.

Most communications applications rely on good frequency accuracy. For example, Ethernet and Fibre Channel specify a frequency drift of no more than +/-100PPM over the lifetime of the equipment. Although quartz crystals can easily accommodate this, engineers must ensure that the mating interface between the crystal and the oscillator circuit is well controlled. Figure 1 shows the electrical model that can be used to calculate the centre frequency of oscillation. The parameters L1 (motional inductance), RR (series resistance), C1 (motional capacitance), and C0 (shunt capacitance) depend upon the crystal design and manufacturing, while CL (load capacitance) depends on intentional and parasitic loading due to external capacitors, on-chip capacitors and stray capacitance of traces and amplifier gates. RNEG (amplifier negative resistance) is determined by the crystal oscillator circuit design and process.

Figure 1. The centre frequency of oscillation for a quartz oscillator depends on multiple parameters including CL which includes stray board and device capacitance.

In most cases, all parameters are well specified by the crystal, capacitor and oscillator suppliers. However, the contribution of parasitic board capacitance is the responsibility of the system design engineer. Equation 1 below shows the effect that a small amount of excess trace capacitance can have. The parameter dFL is the total amount of frequency shift induced by a change in load capacitance (dCL). For nominal values of C1, C0 and CL, a 1pF excess capacitance will change the output frequency by 76PPM. Accounting for typical +/-20PPM temperature drift and some aging, the frequency may wander out of spec. Maintaining a controlled layout and accounting for all parasitics is key to achieving good accuracy. Note that the units of dFL is in PPM, C1 is in fF, while dCL, C0 and CL are in pF.

Equation 1: dFL = 2000×C1×dCL / (C0+CL)²

Figure 2 shows a cascade of PLLs that comprises a typical communications link. The clock generator provides a base clock for the transmitter. That clock gets multiplied to line rate, and the receive PLL locks to the data at line rate and provides a clock for data recovery. The jitter transfer function of each PLL is a low pass filter that tracks the low-frequency component of the clock phase noise but rejects phase noise above the cut-off frequency. This means that only a portion of the clock phase noise impacts the data output onto the channel. The rest is filtered. In many cases, especially considering today’s advanced SERDES designs, the transmitter and receiver have very high cut-off frequencies, sometimes greater than 40MHz. This means much of the clock phase noise will pass through the transmitter clock multiplier and show up on the channel.

Figure 2. The bandwidth of the TX clock multiplier determines the portion of the clock phase jitter that appears on the communications channel.

Because only a portion of the jitter impacts the communications link, ASIC and processor suppliers specify an integration band. For OC-48, the integration band of interest is from 12kHz to 20MHz offset. However, most clock suppliers have standardised on providing 12kHz to 20MHz integrated phase noise as a common figure of merit by which end users can make apples-to-apples comparisons between competing devices. Today’s processors require low phase jitter at wider integration bandwidths, so specifying 12kHz to 40MHz bandwidths on the clock has become necessary.

Total clock phase jitter should account for a small percentage of the overall jitter budget, usually 0.1 to 0.3 of the unit interval. The unit interval of 12Gbps line rates is 83ps. In this case, the total clock jitter should be much less than 8ps peak-to-peak. Accounting for a bit error rate of 10-12 means that the RMS phase jitter should be no more than 0.6ps. For 25Gbps line rates, the recommended RMS clock jitter is 0.3ps.

It is challenging enough to generate such low-phase jitter clocks, but the challenge is compounded by the requirement to fan-out clock signals to multiple devices. Jitter requirements are not confined to the clock generator source but rather refer to the total accumulated jitter through the entire clock tree. This presents the final challenge in today’s system design. Fan-out requirements include those where all the clocks require the same voltage and logic level type. For example, a 4-port 12G Fibre Channel switch may use multiple copies of a 212.5MHz low jitter clock reference, all LVDS logic and all powered from a 2.5V supply. Other devices like FPGAs may require four outputs using LVDS output logic, while two use LVCMOS. In many cases, the fan-out stage may pose a make-or-break, more typically break, condition for meeting jitter.

Equation 2 accounts for the total RMS phase jitter when cascading multiple stages. The total jitter is the root mean square sum of the individual RMS jitter values. When cascading fan-out stages, the end-user must make certain that the RMS phase jitter does not accumulate high enough to degrade the link. Using a clock generator with 0.25ps RMS phase jitter and cascading a fan-out buffer with 0.5ps additive RMS jitter degrades the total performance to 0.56ps RMS. Cascading multiple stages may also introduce jitter due to poor signal integrity or power supply noise.

A quicker, easier and more effective way to implement a clock tree can be found using highly integrated clock generators. Such clock generators with integrated output buffers can ease the burden of calculating accumulated phase jitter across a cascade of components. Such devices accept a low-cost crystal, generate the desired output frequency, multiply if necessary and fan out to multiple clocks. The ability to mix and match output logic types and output supply voltage rails on the same device present an added convenience factor that saves component count and quickens the design. As long as the recommendations for the crystal are closely followed, end users can meet output jitter of 200fs specified at the output of the fan-out stage, including the effects of crosstalk, while maintaining tight frequency accuracy. No calculation for compounded accumulated jitter is necessary.

For the highest level of integration and ease of design, a fully integrated clock generator such as the MX85 provides all the benefits of highly integrated clocks but also integrates the crystal. By integrating the crystal, these devices eliminate design and supply chain issues associated with quartz. The end-user gets a single device with guaranteed output frequency tolerance in a small 5mm x 7mm form factor that generates up to two frequencies. The closely coupled on-chip fan-out stage with ultra-low noise results in an industry-leading 227fs RMS phase jitter, as shown in Figure 3, even for a broad 12kHz to 40MHz integration band. This addresses the requirements on next-generation communications standards while reducing board space and alleviating all the design challenges traditionally imposed by clock and timing.

Figure 3. The MX852BB0030 integrates the entire clock tree, including crystal and fan-out buffers, to achieve an impressive 227fs RMS phase jitter over an extended 12kHz to 40MHz band of integration.

In conclusion

There are several alternatives for meeting the combination of frequency accuracy, ultra-low phase jitter and high fan-out required by next-generation end systems. Today’s highly integrated clocking solutions deliver the performance while avoiding the design risk, complexity and analysis involved in crystal design, quartz crystal supply chain management and cascading multiple PLL clock generators with large fan-out buffers.