Low-jitter clock supports JESD204B in high-speed converters

A two-stage PLL with an integrated JESD204B SYSREF generator for multiple device synchronization - the Analog Devices' AD9528 clock generator is now available from Digi-Key. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low-noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The on-chip VCO tunes from 3.45GHz to 4.025GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices. Applications include high-performance wireless transceivers, LTE and multicarrier GSM base stations, wireless and broadband infrastructure, medical instrumentation, clocking high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs (supports JESD204B), low-jitter / low-phase noise clock distribution, ATE and high-performance instrumentation.