Cadence – New system achieves 40% reduction in PCB place-and-route design

Jul 8 2009 - Design & Manufacture [More Design & Manufacture Articles]

Cadence Design Systems, a leader in global electronic design innovation has announced that the Cadence Global Route Environment (GRE) technology for Cadence Allegro PCB design enabled Hitachi to successfully reduce printed circuit board (PCB) place-and-route design time by 40% for a high-speed communication product.

Hitachi applied the GRE place-and-route design methodology to its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where no automation was previously available. The time-saving results were reported by Hitachi Communication Technologies, Ltd., the communication products division of Hitachi Group, as part of a companywide initiative at Hitachi to enhance design efficiency and reduce design-cycle time.

“High-speed PCBs require significant enhancements in performance, and gigahertz-level signals are becoming common,” said Toru Hiyama, general manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi.

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