Low-cost alternative to CPLDs and FPGAs

A new class of crossover programmable logic device, which supports

applications that traditionally have been addressed either by high-density

CPLDs or low-capacity FPGAs, but with a more comprehensive and

cost-effective architecture and technology, has been announced by Lattice

Semiconductor.

Through the use of 130nm non-volatile embedded Flash process technology, and

the use of an industry-standard 4-input Look-up Table (LUT) approach for

logic implementation, the new devices provide system designers with up to

50% lower cost per logic function, yet deliver a dramatic increase in

features. The first two devices to be made available are the MachXO256 and

MachXO640.

Not content merely to address traditional CPLD applications with the new

MachXO devices, the company has added to all family members distributed

memory, a low standby power Sleep mode and the ability to transparently

update logic configurations through proprietary TransFR (Transparent Field

Reconfiguration)technology. In addition, support for Embedded Block RAM

(EBR) and phase-locked loop (PLL) clock circuitry, as well as PCI and LVDS

I/O, has been added to the larger family members, providing functionality

typically found only in traditional FPGA architectures. At the same time,

the instant on, single-chip and high-speed benefits of previous generations

of Lattice CPLDs, such as its popular MACH devices, have been preserved.

MachXO devices are suitable for the implementation of a wide array of

functions, including bus bridging, interfacing, control logic, clock

management, power and reset control, glue logic, memory control and ASIC and

FPGA configuration. These applications are found in a wide variety of

end-markets, including Automotive, Consumer, Communications, Computing,

Industrial, Medical, Military and Networking.

“When we defined our MachXO products, we took a hard look at the features

that customers needed for control, bus-bridging and interface functions that

are most commonly implemented in CPLDs,” said Stan Kopec, Lattice vice

president of marketing. “It quickly became obvious that by utilising the

efficiency of a LUT-based architecture, and combining it with our unique

high-performance Flash plus SRAM technology, we would be able to provide a

significantly lower cost per function, and to add features that are

extremely important in the implementation of today´s bridging and interface

functions.”

The MachXO logic devices are built on a low cost 130nm embedded Flash

process technology that enables instant-on operation in a single chip, a

feature essential to many CPLD applications. Pin-to-pin delays as fast as

3.5ns allow the devices to address the high-speed requirements of

contemporary system designs. The technology utilizes a native 1.2V logic

core that is supported directly by ´E´ versions of the MachXO devices for

the lowest power consumption. An on-chip voltage regulator allows ´C´

versions of the devices to support 1.8V, 2.5V or 3.3V external power

supplies to support legacy system power requirements.

Four density levels have been defined for the MachXO family, including 256,

640, 1200 and 2280 LUT devices, with user I/O counts ranging from 78 to 271

I/O. Package options include thin quad flatpack (TQFP), 8mm by 8mm

footprint chip-scale BGA (csBGA) and fine-pitch BGA (fpBGA) package styles

from 100 to 324 leads. The MachXO1200 and MachXO2280 support one or two

analog PLLs, as well as one or three 9K-bit embedded block RAM blocks,

respectively, yielding 9.2K or 27.6K bits of block memory per device. Flash

back-up allows each EBR block to be configured not only for standard single-

and dual-port RAM functions, but also non-volatile user ROM. Dedicated

´hard´ FIFO support logic increases the efficiency of FIFO implementations

as well, requiring no additional LUTs for pointer and flag functions.

At the core of each device is an array of look-up tables that can be used to

implement logic and small distributed memories. This array is surrounded by

flexible I/Os that can implement a variety of popular I/O standards such as

LVCMOS and, on the larger devices, PCI and LVDS.

A Sleep mode offers up to a 100x reduction in standby power, supporting

those applications that demand low power. The devices also support the

novel TransFR technology that allows the Flash configuration storage to be

programmed transparently while the device continues to operate normally from

its SRAM configuration storage. The new configuration can be downloaded

when convenient from the Flash to the SRAM blocks in milliseconds. TransFR

technology allows devices to be updated without significantly disrupting

system operation, enabling the flexibility of field logic updates while

maintaining ´5 nines´ (99.999%) or better system availability.

Complete timing driven design for the MachXO devices is included in the

Lattice ispLEVER design tool suite. Mentor Graphics´ Precision RTL

Synthesis and Synplicity´s Synplify synthesis tools support VHDL and Verilog

design entry, and the ispLEVER software provides a comprehensive suite of

implementation, verification and programming tools. The ispLEVER 5.0

Service Pack 1 is available for immediate download from the Lattice web

site. Evaluation boards for the MachXO256 and MachXO640 devices also are

available.